Why do you want to avoid the on-board SATA controller? What is out of control – caches, esp. I suppose I’ll have to try the Jmicron controller, returning the board isn’t really an option as I need on with a serial and parallel port, and there aren’t that many around nowadays. Or sign in with one of these services. At this point in the code, register cl should contain the byte read from PCI configuration register 0xdf.
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When Windows loads it will detect a new hard disk – cancel the wizard for installing the new hardware and run the Intel driver installer you downloaded in step 1.
Hot plug on the ICH9R – Hard Disk Drives (HDD) – StorageReview Forums
The option ROM loads, correctly reports connected drives, and allows booting from them. Edited June 22, by mockingbird.
Posted January 8, But beyond chipset support, what else is needed, and is it even advisable? I don’t know if you guys have arrived at this realization yet or not, but if not, just fyi: Navigation Main page Recent changes Random page. I also used pcicfg in DOS to check the card was detected.
In no case did setting 0xdf cause the JMB to become a multi-function device. Follow the prompts as if you were installing the software:.
The controller is a Jmicron JMB This support is now enabled by default. See also the list of hardware features. Not much help for me anyhow as I don’t plan on using Vista anytime soon. I should have kept a closer watch on this thread. I make jmocron effort to highlight vendors that support their chipsets by posting hardware documentation publicly open hardware.
JMicron JMB363 Add-on Card AHCI mode
There is indeed a checksum byte. Has per-device hardware queues, and supports legacy TCQ. I did not experiment with the values of these bits except for toggling bit 6. Follow the prompts as if you were installing the software: Here is the link: Header Type ‘non-bridge’ single-func Vendor: Jmidron JMicron-specific driver is available only for Windows. Option ROM sets this to either 0xf1 or 0x There appear to be some error handling issues in the nForce4 SATA controllers, where system lockups or machine check exceptions can occur when the driver attempts to access the controller registers as part of hot-pluug handling.
I made changes at three locations: Linux sets register 0x41 to 0xa1, while the option ROM will set it to 0xf1 or 0x Anyway, you can erase the flash chip, so that no option ROM is executed and the card is rendered non-bootable anymore. It’s really upsets me when tech manufacturers claim a feature is present and working while it actually isn’t.
But no point as all Intel chipsets would have the same problem. Similar to ServerWorks “frodo”: Posted August 31, At this point in the code, register cl should contain the byte read from PCI configuration register 0xdf. Register Function 43 Defaults to 0x I used the newest version of the option ROM 1.